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W27L02 256K x 8 ELECTRICALLY ERASABLE EPROM
1. GENERAL DESCRIPTION
The W27L02 is a high speed, low power consumption Electrically Erasable and Programmable Read Only Memory organized as 262,144 x 8 bits. It requires only one supply in the range of 3.3V 10% in normal read mode. The W27L02 provides an electrical chip erase function.
2. FEATURES
* * * * *
Wide range for power supply voltage: 3.3V 10% High speed access time: 70/90 nS (max.) Read operating current: 15 mA (max.) Erase/Programming operating current: 30 mA (max.) Standby current: 20 A (max.)
* * * * *
+12V erase/programming voltage Fully static operation All inputs and outputs directly TTL/CMOS compatible Three-state outputs Available packages: 32-lead PLCC and 32-lead STSOP
3. PIN CONFIGURATIONS
4. BLOCK DIAGRAM
VDD Vss VPP #PGM #CE
CONTROL
AAA 111 256 4 5 6 7 8 9 10 11 12 1 13 4 32
# VVPA p DG1 p DM7 1 3 2 3 1 3 0 29 28 27 26 25 24 23 2 22 0 21
#OE
OUTPUT BUFFER
Q0 . . Q7
A7 A6 A5 A4 A3 A2 A1 A0 Q0
32-lead PLCC
1 5
1 6
11 78
1 9
A14 A13 A8 A9 A11 #OE A10 #CE Q7
A0 . . A17
DECODER
CORE ARRAY
QQVQQQQ 12s3456 s
5. PIN DESCRIPTION
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
A11 A9 A8 A13 A14 A17 #PGM V DD V PP A16 A15 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32-lead STSOP
#OE A10 #CE Q7 Q6 Q5 Q4 Q3 V SS Q2 Q1 Q0 A0 A1 A2 A3
SYMBOL A1 - A17 Q0 - Q7 #CE #OE #PGM VPP VDD Vss NC
DESCRIPTION Address Inputs Data Inputs/Outputs Chip Enable Output Enable Program Enable Program/Erase Supply Voltage Power Supply Ground No Connection
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Publication Release Date: February 20, 2003 Revision A3
W27L02
6. FUNCTIONAL DESCRIPTION
Read Mode
Like conventional UVEPROMs, the W27L02 has two control functions and both of these produce data at the outputs. #CE is for power control and chip select. #OE controls the output buffer to gate data to the output pins. When addresses are stable, the address access time (TACC) is equal to the delay from #CE to output (TCE), and data are available at the outputs TOE after the falling edge of #OE, if TACC and TCE timings are met.
Erase Mode
The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs, which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half an hour), the W27L02 uses electrical erasure. Generally, the chip can be erased within 100 mS by using an EPROM writer with a special erase algorithm. There are two ways to enter Erase mode. One is to raise VPP to VPE (12V), VDD = VCE (5V), #CE low, #OE high, A9 = VHH (12V), and all other address pins are kept at fixed low or high. Pulsing #PGM low starts the erase operation. The other way is somewhat like flash, by programming two consecutive commands into the device and then enter Erase mode. The two commands are loading Data = AA(hex) to Addr. = 5555(hex) and Data = 10(hex) to Addr. = 2AAA(hex). Be careful to note that the #PGM pulse widths of these two commands are different: One is 100 S, while the other is 100 mS. Please refer to the Smart Erase Algorithm 1 & 2.
Erase Verify Mode
After an erase operation, all of the bytes in the chip must be verified to check whether they have been successfully erased to "1" or not. The erase verify mode automatically ensures a substantial erase margin. This mode will be entered after the erase operation if VDD = VPE (5V), #CE low, and #OE low, #PGM high.
Program Mode
Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only way to change cell data from "1" to "0." The program mode is entered when VPP is raised to VPP (12V), VDD = VCP (5V), #CE low, #OE high, the address pins equal the desired addresses, and the input pins equal the desired inputs. Pulsing #PGM low starts the programming operation.
Program Verify Mode
All of the bytes in the chip must be verified to check whether they have been successfully programmed with the desired data or not. Hence, after each byte is programmed, a program verify operation should be performed. The program verify mode automatically ensures a substantial program margin. This mode will be entered after the program operation if VPP = VPP (12V), #CE low, #OE low, and #PGM high.
Erase/Program Inhibit
Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different data. When #CE high , erasing or programming of non-target chips is inhibited, so that except for the #CE, the W27L02 may have common inputs.
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W27L02
Standby Mode
The standby mode significantly reduces VDD current. This mode is entered when #CE high. In standby mode, all outputs are in a high impedance state, independent of #OE and #PGM.
Two-line Output Control
Since EPROMs are often used in large memory arrays, the W27L02 provides two control inputs for multiple memory connections. Two-line control provides for lowest possible memory power dissipation and ensures that data bus contention will not occur.
System Considerations
EPROM power switching characteristics require careful device decoupling. System designers are concerned with three supply current issues: standby current levels (ISB), active current levels (ICC), and transient current peaks produced by the falling and rising edges of #CE. Transient current magnitudes depend on the device output's capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 F ceramic capacitor connected between its VDD and Vss. This high frequency, low inherent-inductance capacitor should be placed as close as possible to the device. Additionally, for every eight devices, a 4.7 F electrolytic capacitor should be placed at the array's power supply connection between VDD and Vss. The bulk capacitor will overcome voltage slumps caused by PC board trace inductances.
Table of Operating Modes
VDD = 3.3V 10%, Vpp = VpE = VHH = 12V, VCP = VPE = VCE = 5V, X = VIH or VIL
MODE Read Output Disable Standby (TTL) Standby (CMOS) Program Program Verify Program Inhibit Erase1 Erase2 Erase Verify Erase Inhibit Product Identifier Manufacturer Product Identifier Device
PINS #CE VIL VIL VIH VDD 0.3V VIL VIL VIH VIL VIL #OE VIL VIH X X VIH VIL X VIH VIH #PGM X X X X VIL VIH X VIL VIL A0 X X X X A9 X X X X OTER ADDR X X X X VDD VDD VDD VDD VDD VCP VCP VCP VCE VCE VCE VPE VCE VDD VDD VPP VDD VDD VDD VDD VPP VPP VPP VPE VCP VCP VPP VPE VDD VDD OUTPUTS DOUT High Z High Z High Z DIN DOUT High Z FF (Hex) AA (Hex) 10 (Hex) DOUT High Z DA (Hex) 85 (Hex)
VIL VIH VIL VIL
VIL X VIL VIL
VIH X X X
X X X X X X X X X VIL VPE First command: Addr. = 5555 (hex) Second command: Addr. = 2AAA (hex) X X X X X X VIL VIH VHH VHH X X
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Publication Release Date: February 20, 2003 Revision A3
W27L02
8. ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER Operation Temperature Storage Temperature Voltage on all Pins with Respect to Ground Except VDD, VPP and A9 Pins Voltage on VDD Pin with Respect to Ground Voltage on VPP Pin with Respect to Ground Voltage on A9 Pin with Respect to Ground RATING 0 to +70 -65 to +125 -0.5 to VDD +0.5 -0.5 to +7.0 -0.5 to +14.5 -0.5 to +14.5 UNIT C C V V V V
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
Capacitance
(VDD = 3.3V 10%, TA = 25 C, f = 1 MHz)
PARAMETER Input Capacitance Output Capacitance
SYMBOL CIN COUT
CONDITIONS VIN = 0V VOUT = 0V
MAX. 6 12
UNIT pF pF
Read Operation DC Characteristics
(VDD = 3.3V 10%, TA = 0 to 70 C)
PARAMETER Input Load Current Output Leakage Current Standby VDD Current (TTL input) Standby VDD Current (CMOS input) VDD Operating Current VPP Operating Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VPP Operating Voltage
SYM. ILI ILO ISB ISB1 ICC IPP VIL VIH VOL VOH VPP
CONDITIONS VIN = 0V to VDD VOUT = 0V to VDD #CE = VIH #CE = VDD 0.2V #CE = VIL, IOUT = 0 mA, f = 5 MHz VPP = VDD IOL = 1.6 mA IOH = -0.1 mA -
LIMITS MIN. -5 -10 -0.3 2.0 2.4 VDD -0.7 TYP. MAX. 5 10 200 20 15 10 0.6 VDD +0.5 0.4 VDD
UNIT A A A A mA A V V V V V
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W27L02
Electrical Chericteristics, continued
Program/Erase DC Characteristics
(TA = 25 C , VDD = 3.3V 10%, VHH = 12V)
PARAMETER Input Load Current VDD Program Current VDD Erase Current VPP Program Current VPP Erase Current Input Low Voltage Input High Voltage Output Low Voltage (Verify) Output High Voltage (Verify) A9 Silicon I.D. Voltage A9 Erase Voltage VPP Program Voltage VPP Erase Voltage VDD Supply Voltage (Program) VDD Supply Voltage (Erase) VDD Supply Voltage (Erase Verify)
SYM. ILI ICP ICE IPP IPE VIL VIH VOL VOH VID VID VPP VPE VCP VCE VPE
CONDITIONS VIN = VIL or VIH #CE = VIL, #OE = VIH, #PGM = VIL #CE = VIL, #OE = VIH, #PGM = VIL, A9 = VHH #CE = VIL, #OE = VIH, #PGM = VIL #CE = VIL, #OE = VIH, #PGM = VIL, A9 = VHH IOL = 2.1 mA IOH = -0.4 mA -
LIMITS MIN. -10 -0.3 2.4 2.4 11.5 11.75 11.75 11.75 4.5 4.5 TYP. 12.0 12.0 12.0 12.0 5.0 5.0 5.0 MAX. 10 30 30 30 30 0.8 5.5 0.45 12.5 14.25 12.25 14.25 5.5 5.5 -
UNIT A mA mA mA mA V V V V V V V V V V V
Note: VDD must be applied simultaneously or before VPP and removed simultaneously or after VPP.
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Publication Release Date: February 20, 2003 Revision A3
W27L02
Electrical Chericteristics, continued
AC Test Conditions
PARAMETER Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load 0V to 3.0V 5 nS 1.5V/1.5V CL = 100 pF, IOH/IOL = -0.1 mA/1.6 mA for Read IOH/IOL = -0.4 mA/2.1 mA for Program/Erase CONDITIONS
AC Test Load and Waveforms
+1.3V (IN914)
3.3K ohm
DOUT
100 pF (Including Jig and Scope)
Input
Test Points 3.0V
1.5V
Output
Test Points
1.5V
0V
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W27L02
Electrical Chericteristics, continued
Read Operation AC Characteristics
(VDD = 3.3V 10%, TA = 0 to 70 C)
PARAMETER Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time #OE High to High-Z Output Output Hold from Address Change
SYM. TRC TCE TACC TOE TDF TOH
W27L02-70 MIN. 70 0 MAX. 70 70 30 25 -
W27L02-90 MIN. 90 0 MAX. 90 90 40 25 -
UNIT nS nS nS nS nS nS
Note: VDD must be applied simultaneously or before VPP and removed simultaneously or after VPP.
AC Programming/Erase Characteristics
(VDD = 3.3V 10%, TA = 25 C )
PARAMETER VPP Setup Time Address Setup Time Data Setup Time #PGM Program Pulse Width #PGM Erase Pulse Width Data Hold Time #OE Setup Time Data Valid from #OE #OE High to Output High Z Address Hold Time after #PGM High Address Hold Time (Erase) #CE Setup Time
SYM. TVPS TAS TDS TPWP TPWE TDH TOES TOEV TDFP TAH TAHE TCES
LIMITS MIN. 2.0 2.0 2.0 95 95 2.0 2.0 0 0 2.0 2.0 TYP. 100 100 MAX. 105 105 150 130 -
UNIT S S S S mS S S nS nS S S S
Note: VDD must be applied simultaneously or before VPP and removed simultaneously or after VPP.
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Publication Release Date: February 20, 2003 Revision A3
W27L02
9. TIMING WAVEFORMS
AC Read Waveform
VIH Address VIL VIH #CE VIL Address Valid
TCE
VIH #OE VIL TACC Outputs High Z Valid Output High Z TOE TDF TOH
Program Waveform
Program VIH Address VIL TAS Data Data In Stable TDS 12.0V VPP 5.0V #CE VIH VIL TDH Address Stable
Program Verify Address Stable TDFP
Read Verify Address Valid
TACC DOUT DOUT
DOUT
TAH
5.0V TVPS TCES
TOE #OE VIH VIL VIH #PGM VIL TPWP TOES
TOEV
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W27L02
Timing Waveforms, Continued
Erase Waveform 1
Read Manufacturer Read Device Chip Erase A9 = 12.0V Others = V IL Address Stable TAS TAHC Data All One TDS 12.0V 5.0V VPP VIH VIL TOE #OE VIH VIL TCES TPWE TOEV TOE TOES TOE TCE TVPS TDH TDFP DOUT T AH DOUT Address Stable Address Stable TACC DOUT Erase Verify Blank Check Read Verify SID SID A9 = 12.0V VIH VIL Others = VIL A0 = V IL TAS
A0=VIH Others= IL V
Address
TAS
Data
DA
85
= VDD
#CE
#PGM
Erase Waveform 2
Read Manufacturer Read Device Chip Erase Erase Verify Blank Check Read Verify SID SID A9 = 12.0V VIH VIL Others = VIL A0 = V IL TAS
A0=VIH Others= IL V
Command 1 5555 TAS
Command 2 2AAA TAHC Address Stable TDFP DOUT TDH T AH DOUT Address Stable Address Stable TACC DOUT
Address
TAS
Data
DA
85
TDS
AA
10
12.0V 5.0V VPP VIH #CE VIL TOE #OE VIH VIL TCES #PGM TPWP TPWP TOEV TOE TOES TCE TVPS
= VDD
TOE
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Publication Release Date: February 20, 2003 Revision A3
W27L02
10. SMART PROGRAMMING ALGORITHM
Start
Address = First Location
VDD = 5V Vpp = 12V
X=0
Program One 100 S Pulse
Increment X Yes
X = 25? No Fail Verify One Byte Pass Increment Address No Last Address? Yes VDD = 5V Vpp = 5V
Verify One Byte Pass
Fail
Compare All Bytes to Original Data Pass Pass Device
Fail
Fail Device
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W27L02
11. SMART ERASE ALGORITHM 1
Start X=0
VDD = 5V Vpp = 12V
A9 = 12V; A0 = V IL Chip Erase 100 mS Pulse
Address = First Location
VDD = 3.0V Vpp = 3.0V
Increment X No
Compare All Bytes to FFs (HEX) Pass Pass Device
Fail
X = 20? Yes Fail Device
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Publication Release Date: February 20, 2003 Revision A3
W27L02
12. SMART ERASE ALGORITHM 2
Start X=0
VDD = 5V Vpp = 12V
Command 100uS Pulse with Address = 5555(Hex) Data = AA(Hex) Command 100mS Pulse with Address =2AAA(Hex) Data = 10(Hex)
Address = First Location
VDD = 3.0V Vpp = 3.0V
Increment X No
Compare All Bytes to FFs (HEX) Pass Pass Device
Fail
X = 20? Yes Fail Device
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W27L02
13. ORDERING INFORMATION
PART NO. ACCESS TIME (nS) 70 90 70 90 POWER SUPPLY CURRENT MAX. (mA) 15 15 15 15 STANDBY VDD CURRENT MAX. (A) 20 20 20 20 PACKAGE
W27L02P-70 W27L02P-90 W27L02Q-70 W27L02Q-90
Notes:
32-Lead PLCC 32-Lead PLCC 32-Lead STSOP 32-Lead STSOP
1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.
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Publication Release Date: February 20, 2003 Revision A3
W27L02
14. PACKAGE DIMENSIONS
32-Lead PLCC
HE E
4
1
32
30
Symbol
5 29
Dimension in Inches
Dimension in mm
Min. Nom. Max.
0.140 0.020 0.105 0.026 0.016 0.008 0.547 0.447 0.044 0.490 0.390 0.585 0.485 0.075 0.110 0.028 0.018 0.010 0.550 0.450 0.050 0.510 0.410 0.590 0.490 0.090 0.115 0.032 0.022 0.014 0.553 0.453 0.056 0.530 0.430 0.595 0.495 0.095 0.004 0 10
Min. Nom. Max.
3.56 0.50 2.67 0.66 0.41 0.20 13.89 11.35 1.12 12.45 9.91 14.86 12.32 1.91 2.80 0.71 0.46 0.25 13.97 11.43 1.27 12.95 10.41 14.99 12.45 2.29 2.93 0.81 0.56 0.35 14.05 11.51 1.42 13.46 10.92 15.11 12.57 2.41 0.10 0 10
D
H
D
G
D
13
21
14
20
c
A A1 A2 b1 b c D E e GD GE HD HE L y Notes:
L A
2
A
Seating Plane
e
b b1 GE
A y
1
1. Dimensions D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches. 4. General appearance spec. should be based onfinal visual inspection sepc.
32-Lead STSOP (8 x 14 mm)
HD D c
Dimension in Inches Dimension in mm Symbol Min. Nom. Max. Min. Nom. Max.
1.20 0.05 0.95 0.17 0.10 1.00 0.22 ----12.40 8.00 14.00 0.50 0.028 0.50 0.60 0.80 0.004 3 5 0.00 0 3 0.10 5 0.70 0.15 1.05 0.27 0.21
e
E
b
L L1
A1 A2 A
Y
A A1 A2 b c D E HD e L L1 Y
0.047 0.002 0.035 0.007 0.004 0.040 0.009 ----0.488 0.315 0.551 0.020 0.020 0.000 0 0.024 0.031 0.006 0.041 0.010 0.008
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W27L02
15. VERSION HISTORY
VERSION A1 A2 DATE Oct. 19, 2001 May 30, 2002 PAGE 10 2, 3, 4, 6 3 All A3 Feb. 20, 2003 1, 13, 14 Initial Issue Modify Erase Waveform Correct the Vcv(VPP) as VPE(VPP) under Erase Inhibit Mode Modify the Pin of VPP from VPE to VPP In the Erase Verify Mode Delete VDD = 5.0V 10% Delete DIP package DESCRIPTION
Headquarters
No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/
Winbond Electronics Corporation America
2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798
Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998
Taipei Office
9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
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Publication Release Date: February 20, 2003 Revision A3

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